HTC Global Services hiring #Freshers
Role : #Developer
Designation: Programmer Analyst Trainee
Email Id: Joseline.Raveendran@htcindia.com
Interested candidates send your scanned docs of your 10th & 12th marks sheet, Consolidated mark sheet, Aadhaar card and
Job description:
- Good understanding on Java,SQL and other technical concepts.
- Be a strong team player and collaborate to ensure success of the team.
- Excellent written and verbal communication skills.
- Manage multiple project and personal priorities simultaneously.
Eligibility criteria:
Year of passing-2018,2019 & 2020
Age-Below 25 yrs
Qualification- B.E, B.tech
computer science, ECE, EEE, IT, BCA, MCA,
B.sc
computer science, Electronics, Mathematics, Physics, Statistics, Information science, Information technology.
CTC-3 lakhs per annum
Role : #Developer
Designation: Programmer Analyst Trainee
Email Id: Joseline.Raveendran@htcindia.com
Interested candidates send your scanned docs of your 10th & 12th marks sheet, Consolidated mark sheet, Aadhaar card and
Job description:
- Good understanding on Java,SQL and other technical concepts.
- Be a strong team player and collaborate to ensure success of the team.
- Excellent written and verbal communication skills.
- Manage multiple project and personal priorities simultaneously.
Eligibility criteria:
Year of passing-2018,2019 & 2020
Age-Below 25 yrs
Qualification- B.E, B.tech
computer science, ECE, EEE, IT, BCA, MCA,
B.sc
computer science, Electronics, Mathematics, Physics, Statistics, Information science, Information technology.
CTC-3 lakhs per annum
Excellent Opportunity For #M.Tech #Trained #Freshers For #Noida Location :
1: #RTL Design Engineer
2: #Verification Engineer
3: #DFT Engineer
4: #Embedded Engineer ( #Preferred if you are in #North Location only)
5: #Physical Design Engineers (Preferred if you are in #North Location only) Please share your resume on madhuri.tomar@incise.in
1: #RTL Design Engineer
2: #Verification Engineer
3: #DFT Engineer
4: #Embedded Engineer ( #Preferred if you are in #North Location only)
5: #Physical Design Engineers (Preferred if you are in #North Location only) Please share your resume on madhuri.tomar@incise.in
SocBridge is hiring for Embedded Software Engineers.
Skills: Strong C, C++, Microcontrollers, Linux (having zynq SoC experience is an added advantage)
Experience:0-6yrs(trained freshers or experienced candidates only)
Eligibility: B.TECH/M.TECH
Interested candidates can share your profiles to careers.embedded@socbridgesemi.com
#jobopening #freshers #goodopportunity #hiring
Skills: Strong C, C++, Microcontrollers, Linux (having zynq SoC experience is an added advantage)
Experience:0-6yrs(trained freshers or experienced candidates only)
Eligibility: B.TECH/M.TECH
Interested candidates can share your profiles to careers.embedded@socbridgesemi.com
#jobopening #freshers #goodopportunity #hiring
👍5
Excellent Opportunity for #VLSI Trained #Freshers to work
with Design IP R&D Team at Cadence, Noida/Bangalore.
Position: IP Design Verification Trainee + Intern (Multiple
Positions)
Experience: 0 Years (Freshers from 2022 or 2023 batch)
Qualification: B.Tech/M.Tech (EE/EC/CS) with CGPA > 7/10
Mandatory Skills: Strong understanding of Verilog, SV, UVM,
C++/OOPS and Digital Design concepts.
Salary: 4.8 5.4 LPA
Send your resume to: cdn_dip_hiring@cadence.com
with Subject line: "Internship I Degree: <B.Tech./M.Tech.>
I Year of Passing: |
Preferred Location: <Noida/Bangalore>"
with Design IP R&D Team at Cadence, Noida/Bangalore.
Position: IP Design Verification Trainee + Intern (Multiple
Positions)
Experience: 0 Years (Freshers from 2022 or 2023 batch)
Qualification: B.Tech/M.Tech (EE/EC/CS) with CGPA > 7/10
Mandatory Skills: Strong understanding of Verilog, SV, UVM,
C++/OOPS and Digital Design concepts.
Salary: 4.8 5.4 LPA
Send your resume to: cdn_dip_hiring@cadence.com
with Subject line: "Internship I Degree: <B.Tech./M.Tech.>
I Year of Passing: |
Preferred Location: <Noida/Bangalore>"
👍10❤4
#Insemi Technology is Hiring for DFT #Freshers.
Location- Bangalore
Experience – Freshers
Qualification - B.Tech, M.Tech 2022, 2023 Passed Out.
Skills Required:
Digital Electronics
Verilog/VHDL
CMOS Fundamentals
Scripting Language
Kindly share your updated resume to this mail- annapurneshwari.h@insemitech.com
Location- Bangalore
Experience – Freshers
Qualification - B.Tech, M.Tech 2022, 2023 Passed Out.
Skills Required:
Digital Electronics
Verilog/VHDL
CMOS Fundamentals
Scripting Language
Kindly share your updated resume to this mail- annapurneshwari.h@insemitech.com
❤5👍3
Greetings from SISOC Semiconductor Technologies Pvt Ltd!!
Hiring for hashtag#trained B TECH(2017,2018,2019 and 2020)/ MTECH(2017,2018,2019,2020 and 2021) hashtag#freshers
Eligibility: B Tech/BE (ECE/EEE) / MTech (VLSI/ECE) in hashtag#designverification (Trained or intern)
Open Position :
1.Verification Engineer
Work Location: Bangalore
Skills required :
1. Very Strong knowledge of System Verilog and UVM.
2. Good communication Skills.
3. Minimum 6 months Trained or intern in design verification.
Interested, Kindly share resumes to
mounika.immadi@sisocsemi.com
Hiring for hashtag#trained B TECH(2017,2018,2019 and 2020)/ MTECH(2017,2018,2019,2020 and 2021) hashtag#freshers
Eligibility: B Tech/BE (ECE/EEE) / MTech (VLSI/ECE) in hashtag#designverification (Trained or intern)
Open Position :
1.Verification Engineer
Work Location: Bangalore
Skills required :
1. Very Strong knowledge of System Verilog and UVM.
2. Good communication Skills.
3. Minimum 6 months Trained or intern in design verification.
Interested, Kindly share resumes to
mounika.immadi@sisocsemi.com
❤3👍1
#PhysicalDesign hashtag#Freshers #2022/23 hashtag#Bangalore
We are looking for freshers in Physical Design who are passionate about VLSI and have undergone formal training in Physical Design concepts.
Eligibility Criteria:
B.E./B.Tech/M.E./M.Tech in Electronics/ECE/EEE or related field
Passed out in 2022 or 2023.
Must have completed training in Physical Design (from reputed institute/training partner)
Good understanding of basic Physical Design flow: Floorplanning, Placement, CTS, Routing, STA, DRC/LVS
Strong fundamentals in CMOS, Timing Concepts, and Digital Electronics
Good communication and problem-solving skills
Send your updated resume to mamatha.vedamuri@gaafetsemi.com
We are looking for freshers in Physical Design who are passionate about VLSI and have undergone formal training in Physical Design concepts.
Eligibility Criteria:
B.E./B.Tech/M.E./M.Tech in Electronics/ECE/EEE or related field
Passed out in 2022 or 2023.
Must have completed training in Physical Design (from reputed institute/training partner)
Good understanding of basic Physical Design flow: Floorplanning, Placement, CTS, Routing, STA, DRC/LVS
Strong fundamentals in CMOS, Timing Concepts, and Digital Electronics
Good communication and problem-solving skills
Send your updated resume to mamatha.vedamuri@gaafetsemi.com
❤3
How to Craft a Cover Letter? ✅
https://www.linkedin.com/posts/ajsinghrawat_coverletter-careertips-jobsearch-activity-7365718362984804352-9ow1?utm_source=share&utm_medium=member_desktop&rcm=ACoAAC56xN8By89mq2GxCVC8oMvC-W4wf-EFIrI
https://www.linkedin.com/posts/ajsinghrawat_coverletter-careertips-jobsearch-activity-7365718362984804352-9ow1?utm_source=share&utm_medium=member_desktop&rcm=ACoAAC56xN8By89mq2GxCVC8oMvC-W4wf-EFIrI
Linkedin
#coverletter #careertips #jobsearch #hiring #resumetips #freshers | Ajay Singh Rawat
✍️ Easy Cover Letter Format ✅
If you don’t know where to start, here’s a simple structure anyone can follow:
💡 Pro tip: Keep it 1 page max, easy to read, and specific to the role.
🔖 Save this format for when you apply next!
#CoverLetter #CareerTips #JobSearch…
If you don’t know where to start, here’s a simple structure anyone can follow:
💡 Pro tip: Keep it 1 page max, easy to read, and specific to the role.
🔖 Save this format for when you apply next!
#CoverLetter #CareerTips #JobSearch…