#Hiring #IP & #SOC #Verification Engineers
Experience: 1.5+ years(Relevant Experience- Excluding internships & trainings)
Notice Period: Immediate to 1 Month
Location: #Bangalore/ #Noida/ #Hyderabad/ #Pune
Interested candidates can share their resume at, medha.gaur@truechip.net
Experience: 1.5+ years(Relevant Experience- Excluding internships & trainings)
Notice Period: Immediate to 1 Month
Location: #Bangalore/ #Noida/ #Hyderabad/ #Pune
Interested candidates can share their resume at, medha.gaur@truechip.net
#Hiring Candidate's for CCNA Freshers-Networking Profile for Mumbai and Pune Location Urgently.
Mandatory:--
*Graduation Must.
* CCNA CCNP Qualified or Certified.(From any Institute).
* Networking Fundamentals must be cleared.
* Only Candidates from West Region Mumbai &Pune can Apply to this Profile Strictly.
Skill Set Required:--
*Good Knowledge in configuring Routers and Switches.
* Good knowledge of LAN,WAN, MAN.
* Knowledge of networking fundamental and firewalls.
*Aspiring for a challenging work environment that encourages continuous Learning.
* Utilize technical capability, provide exposure to new ideas/technology.
Please Note:-- All the Candidature Interested for the Above Profile can share their Updated Resumes on below Email-ID.
vrushali.rajput@velocis.co.in
Mandatory:--
*Graduation Must.
* CCNA CCNP Qualified or Certified.(From any Institute).
* Networking Fundamentals must be cleared.
* Only Candidates from West Region Mumbai &Pune can Apply to this Profile Strictly.
Skill Set Required:--
*Good Knowledge in configuring Routers and Switches.
* Good knowledge of LAN,WAN, MAN.
* Knowledge of networking fundamental and firewalls.
*Aspiring for a challenging work environment that encourages continuous Learning.
* Utilize technical capability, provide exposure to new ideas/technology.
Please Note:-- All the Candidature Interested for the Above Profile can share their Updated Resumes on below Email-ID.
vrushali.rajput@velocis.co.in
NVIDIA is #hiring
As requested by many of you i am adding details about the roles below and reopening the Google form. Interested folks kindly fill in the form and attach your resume in there.
Vacancies in ASIC DV / Physical Design / Power teams.
Candidates : From ASIC/ Hardware background.
Discipline : Bachelors/ Masters - EE/ECE/VLSI/Microelectronics
Some areas of work include, ASIC design/ Verification, UVM, System Verilog, Computer Architecture, Low Power techniques, Physical Design methodologies/ ICC2/ Innovus
Link to form - https://lnkd.in/gyjw8ndC
PS: Those who already filled the form earlier need not do it again. Those missed out kindly fill it ASAP.
As requested by many of you i am adding details about the roles below and reopening the Google form. Interested folks kindly fill in the form and attach your resume in there.
Vacancies in ASIC DV / Physical Design / Power teams.
Candidates : From ASIC/ Hardware background.
Discipline : Bachelors/ Masters - EE/ECE/VLSI/Microelectronics
Some areas of work include, ASIC design/ Verification, UVM, System Verilog, Computer Architecture, Low Power techniques, Physical Design methodologies/ ICC2/ Innovus
Link to form - https://lnkd.in/gyjw8ndC
PS: Those who already filled the form earlier need not do it again. Those missed out kindly fill it ASAP.
SocBridge is hiring for Embedded Software Engineers.
Skills: Strong C, C++, Microcontrollers, Linux (having zynq SoC experience is an added advantage)
Experience:0-6yrs(trained freshers or experienced candidates only)
Eligibility: B.TECH/M.TECH
Interested candidates can share your profiles to careers.embedded@socbridgesemi.com
#jobopening #freshers #goodopportunity #hiring
Skills: Strong C, C++, Microcontrollers, Linux (having zynq SoC experience is an added advantage)
Experience:0-6yrs(trained freshers or experienced candidates only)
Eligibility: B.TECH/M.TECH
Interested candidates can share your profiles to careers.embedded@socbridgesemi.com
#jobopening #freshers #goodopportunity #hiring
We are #Hiring an MTech 2023 batch candidate with 0-1 year of experience in C programming for our VIP R&D team in #Noida.
The ideal candidate should have an excellent academic background and be interested in working on C programming, SV/UVM, and verification protocols.
If you meet the eligibility criteria and are passionate about this opportunity, we would love to hear from you. Apply now! share resume on shivansv@cadence.com immediately.
The ideal candidate should have an excellent academic background and be interested in working on C programming, SV/UVM, and verification protocols.
If you meet the eligibility criteria and are passionate about this opportunity, we would love to hear from you. Apply now! share resume on shivansv@cadence.com immediately.
Helloo Everyone!!!
#Immediate hashtag#hiring
We are looking for PD,AL,DV trained freshers from
(2022-2023 )passing year
North based candidates please apply
ping me on linked in or jenith.samson@digicomm.org
#Immediate hashtag#hiring
We are looking for PD,AL,DV trained freshers from
(2022-2023 )passing year
North based candidates please apply
ping me on linked in or jenith.samson@digicomm.org
Greetings from #Garudaven Pvt Ltd
We are immediate #Hiring for #VLSI engineers for Physical Design Trained Freshers for (WFO)
B.Tech 2021 / 2020 / 2019 / 2018
Location: Bangalore / Hyderabad /
Interested Candidates, Please share with me your updated profile to anusha@garudaven.in / madhavi@garudaven.in
We are immediate #Hiring for #VLSI engineers for Physical Design Trained Freshers for (WFO)
B.Tech 2021 / 2020 / 2019 / 2018
Location: Bangalore / Hyderabad /
Interested Candidates, Please share with me your updated profile to anusha@garudaven.in / madhavi@garudaven.in
Mirafra Technologies #Hiring #DFT_DIRECTOR at #Bengaluru Location.
Please find the Job description Below:
Position: DFT Director – Design for Testability (DFT)
Location: Bangalore
Experience Level: 14+ years in semiconductor design, with extensive expertise in DFT methodologies
About the Role
We are seeking a seasoned leader to spearhead our Design for Testability (DFT) division. The DFT Director will play a pivotal role in defining, developing, and growing our DFT capabilities, ensuring we remain at the forefront of semiconductor design services. This individual will oversee project delivery, team development, and client engagement, driving excellence and innovation in DFT methodologies.
Key Qualifications:
Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
14+ years of experience in semiconductor design, with at least 5 years in a leadership role focusing on DFT.
Deep expertise in DFT methodologies, including:
Scan-based testing, ATPG, and fault simulation.
Built-In Self-Test (BIST) techniques.
Test compression and low-power testing.
DFT for hierarchical and multi-die designs.
Proven track record of successful client engagements and project delivery.
Strong leadership, communication, and business acumen.
Familiarity with industry-standard tools such as Mentor Tessent Synopsys Tetramax, , or Cadence Modus.
Preferred Skills:
Experience with multi-site and global team management.
Hands-on experience with post-silicon debug and ATE testing.
Strong understanding of emerging trends in AI-driven test automation and DFT for advanced nodes (e.g., 5nm, 3nm).
Interested candidates can share resume at sayantikamajumdar@mirafra.com
Please find the Job description Below:
Position: DFT Director – Design for Testability (DFT)
Location: Bangalore
Experience Level: 14+ years in semiconductor design, with extensive expertise in DFT methodologies
About the Role
We are seeking a seasoned leader to spearhead our Design for Testability (DFT) division. The DFT Director will play a pivotal role in defining, developing, and growing our DFT capabilities, ensuring we remain at the forefront of semiconductor design services. This individual will oversee project delivery, team development, and client engagement, driving excellence and innovation in DFT methodologies.
Key Qualifications:
Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
14+ years of experience in semiconductor design, with at least 5 years in a leadership role focusing on DFT.
Deep expertise in DFT methodologies, including:
Scan-based testing, ATPG, and fault simulation.
Built-In Self-Test (BIST) techniques.
Test compression and low-power testing.
DFT for hierarchical and multi-die designs.
Proven track record of successful client engagements and project delivery.
Strong leadership, communication, and business acumen.
Familiarity with industry-standard tools such as Mentor Tessent Synopsys Tetramax, , or Cadence Modus.
Preferred Skills:
Experience with multi-site and global team management.
Hands-on experience with post-silicon debug and ATE testing.
Strong understanding of emerging trends in AI-driven test automation and DFT for advanced nodes (e.g., 5nm, 3nm).
Interested candidates can share resume at sayantikamajumdar@mirafra.com
🚀 AndGate Informatics Pvt. Ltd. is hashtag#hiring hashtag#PV hashtag#engineers 🚀
Position: Physical Verification (PV) Engineer
Experience: 4-6 Years
Tool Expertise: Innovus
Notice Period: Immediate Joiners Preferred
Location: Bangalore (BLR)
📩 Apply Now: Send your updated resume to Priyanka.singh@andgatetech.com
Position: Physical Verification (PV) Engineer
Experience: 4-6 Years
Tool Expertise: Innovus
Notice Period: Immediate Joiners Preferred
Location: Bangalore (BLR)
📩 Apply Now: Send your updated resume to Priyanka.singh@andgatetech.com
Mirafra Technologies #Hiring #DFT_DIRECTOR at #Bengaluru Location.
Please find the Job description Below:
Position: DFT Director – Design for Testability (DFT)
Location: Bangalore
Experience Level: 14+ years in semiconductor design, with extensive expertise in DFT methodologies
About the Role
We are seeking a seasoned leader to spearhead our Design for Testability (DFT) division. The DFT Director will play a pivotal role in defining, developing, and growing our DFT capabilities, ensuring we remain at the forefront of semiconductor design services. This individual will oversee project delivery, team development, and client engagement, driving excellence and innovation in DFT methodologies.
Key Qualifications:
Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
14+ years of experience in semiconductor design, with at least 5 years in a leadership role focusing on DFT.
Deep expertise in DFT methodologies, including:
Scan-based testing, ATPG, and fault simulation.
Built-In Self-Test (BIST) techniques.
Test compression and low-power testing.
DFT for hierarchical and multi-die designs.
Proven track record of successful client engagements and project delivery.
Strong leadership, communication, and business acumen.
Familiarity with industry-standard tools such as Mentor Tessent Synopsys Tetramax, , or Cadence Modus.
Preferred Skills:
Experience with multi-site and global team management.
Hands-on experience with post-silicon debug and ATE testing.
Strong understanding of emerging trends in AI-driven test automation and DFT for advanced nodes (e.g., 5nm, 3nm).
Interested candidates can share resume at sayantikamajumdar@mirafra.com
You can reach out to me at +91 - 9007115796.
Please find the Job description Below:
Position: DFT Director – Design for Testability (DFT)
Location: Bangalore
Experience Level: 14+ years in semiconductor design, with extensive expertise in DFT methodologies
About the Role
We are seeking a seasoned leader to spearhead our Design for Testability (DFT) division. The DFT Director will play a pivotal role in defining, developing, and growing our DFT capabilities, ensuring we remain at the forefront of semiconductor design services. This individual will oversee project delivery, team development, and client engagement, driving excellence and innovation in DFT methodologies.
Key Qualifications:
Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
14+ years of experience in semiconductor design, with at least 5 years in a leadership role focusing on DFT.
Deep expertise in DFT methodologies, including:
Scan-based testing, ATPG, and fault simulation.
Built-In Self-Test (BIST) techniques.
Test compression and low-power testing.
DFT for hierarchical and multi-die designs.
Proven track record of successful client engagements and project delivery.
Strong leadership, communication, and business acumen.
Familiarity with industry-standard tools such as Mentor Tessent Synopsys Tetramax, , or Cadence Modus.
Preferred Skills:
Experience with multi-site and global team management.
Hands-on experience with post-silicon debug and ATE testing.
Strong understanding of emerging trends in AI-driven test automation and DFT for advanced nodes (e.g., 5nm, 3nm).
Interested candidates can share resume at sayantikamajumdar@mirafra.com
You can reach out to me at +91 - 9007115796.
📢 📢
hashtag
#Hiring Alert! Qualcomm has exciting job opportunities in Noida, Hyderabad, Chennai and Bangalore.
Noida Openings:
3069345 STA Engineer- 3 to 8 Years
3064801 Staff CPU RTL Design Engineer- 8 to 12 Years
3067605 CPU Physical Design Engineer- 2 to 6 Years
3065121 CPU Lead Physical Design Engineer- 5 to 8 Years
3065116 CPU Staff Physical Design Engineer- 8 to 12 years
3069895 Senior Physical Design Engineer- 3 to 5 years
3069904 Senior Physical Design Engineer- 3 to 5 years
3069896 Staff Physical Design Engineer- 8 to 12 years
3064369 CPU RTL Power management Design Engineer- 10 to 15 years
3069893 Senior DFT Engineer- 3 to 6 years
3061987 Engineer - DFT- 3 to 6 years
3069341 Senior Design Verification Engineer- 2 to 5 years
Bangalore openings:
3070003 Senior Staff Verification Engineer- 12 to 15 years
3067261 IT Support Analyst (Hardware Asset Management)- 5 to 10 years
3060194 AutoIT Solutioning Engineer Staff- 8 to 15 Years
3067240 MSIP Digital Design Engineer- 2 to 6 Years
3063658 MSIP Digital Design Engineer- 8 to 12 years
3068889 Lead/Staff Digital Design Engineer- 5 to 12 years
3063644 IT Service Resilience Manager- 12 to 16 years
3068849 Lead/Staff Analog Modeling, verification and Characterization Engineer- 5 to 12 years
3063457 SAP FI/CO Consultant- 3 to 10 years
3067241 Senior IT Engineer (Desktop Field Services)- 8 to 12 years
3069437 Engineering IT Software Solutions Manager- 8 to 12 years
3069054 Staff HPC Software Developer- 12 to 15 years
3065265 PMIC Lead Layout Engineer- 5 to 8 years
3065266 PMIC Staff Layout Engineer- 8 to 12 years
3067488 Staff Design Verification- 8 to 12 years
3069507 Full Stack Developer, Staff- 10 to 15 years
Hyderabad Openings:
3067257 Lead AV(Audio Visual) Engineer- 5 to 10 years
3066680 Quantum Leap - IT Project Manager, Associate- 12 to 18 Years
3066681 Quantum Leap - IT Project Manager (Cyber Security)- 12 to 18 years
3065904 Cyber Threat Response Engineer- 2 to 6 years
3067307 Cyber Threat Research Engineer, Senior- 5 to 10 years
3066679 IT Support Analyst, Senior- 5 to 10 years
Chennai openings:
3067254 AV(Audio Visual) Engineer- 2 to 6 years
If you are ready to be part of our innovative team, submit your resume/CV today 👉 kumaami@qti.qualcomm.com.
Career site link: https://lnkd.in/gWg8MRdW
hashtag
#Hiring Alert! Qualcomm has exciting job opportunities in Noida, Hyderabad, Chennai and Bangalore.
Noida Openings:
3069345 STA Engineer- 3 to 8 Years
3064801 Staff CPU RTL Design Engineer- 8 to 12 Years
3067605 CPU Physical Design Engineer- 2 to 6 Years
3065121 CPU Lead Physical Design Engineer- 5 to 8 Years
3065116 CPU Staff Physical Design Engineer- 8 to 12 years
3069895 Senior Physical Design Engineer- 3 to 5 years
3069904 Senior Physical Design Engineer- 3 to 5 years
3069896 Staff Physical Design Engineer- 8 to 12 years
3064369 CPU RTL Power management Design Engineer- 10 to 15 years
3069893 Senior DFT Engineer- 3 to 6 years
3061987 Engineer - DFT- 3 to 6 years
3069341 Senior Design Verification Engineer- 2 to 5 years
Bangalore openings:
3070003 Senior Staff Verification Engineer- 12 to 15 years
3067261 IT Support Analyst (Hardware Asset Management)- 5 to 10 years
3060194 AutoIT Solutioning Engineer Staff- 8 to 15 Years
3067240 MSIP Digital Design Engineer- 2 to 6 Years
3063658 MSIP Digital Design Engineer- 8 to 12 years
3068889 Lead/Staff Digital Design Engineer- 5 to 12 years
3063644 IT Service Resilience Manager- 12 to 16 years
3068849 Lead/Staff Analog Modeling, verification and Characterization Engineer- 5 to 12 years
3063457 SAP FI/CO Consultant- 3 to 10 years
3067241 Senior IT Engineer (Desktop Field Services)- 8 to 12 years
3069437 Engineering IT Software Solutions Manager- 8 to 12 years
3069054 Staff HPC Software Developer- 12 to 15 years
3065265 PMIC Lead Layout Engineer- 5 to 8 years
3065266 PMIC Staff Layout Engineer- 8 to 12 years
3067488 Staff Design Verification- 8 to 12 years
3069507 Full Stack Developer, Staff- 10 to 15 years
Hyderabad Openings:
3067257 Lead AV(Audio Visual) Engineer- 5 to 10 years
3066680 Quantum Leap - IT Project Manager, Associate- 12 to 18 Years
3066681 Quantum Leap - IT Project Manager (Cyber Security)- 12 to 18 years
3065904 Cyber Threat Response Engineer- 2 to 6 years
3067307 Cyber Threat Research Engineer, Senior- 5 to 10 years
3066679 IT Support Analyst, Senior- 5 to 10 years
Chennai openings:
3067254 AV(Audio Visual) Engineer- 2 to 6 years
If you are ready to be part of our innovative team, submit your resume/CV today 👉 kumaami@qti.qualcomm.com.
Career site link: https://lnkd.in/gWg8MRdW
LinkedIn
LinkedIn Login, Sign in | LinkedIn
Login to LinkedIn to keep in touch with people you know, share ideas, and build your career.