Excellent Opportunity For #M.Tech #Trained #Freshers For #Noida Location :
1: #RTL Design Engineer
2: #Verification Engineer
3: #DFT Engineer
4: #Embedded Engineer ( #Preferred if you are in #North Location only)
5: #Physical Design Engineers (Preferred if you are in #North Location only) Please share your resume on madhuri.tomar@incise.in
1: #RTL Design Engineer
2: #Verification Engineer
3: #DFT Engineer
4: #Embedded Engineer ( #Preferred if you are in #North Location only)
5: #Physical Design Engineers (Preferred if you are in #North Location only) Please share your resume on madhuri.tomar@incise.in
Hi All,
Insemi is hiring #Trained Verification engineers.
Please share your resume to joseph.raj@insemitech.com
Insemi is hiring #Trained Verification engineers.
Please share your resume to joseph.raj@insemitech.com
Hi all,
Greetings from Juntran Technologies
We are hiring < 2020 #Trained_Freshers candidates in #vlsi domain for below requirements
#DESIGN_FOR_TESTABILITY
#DESIGN_AND_VERIFICATION
#RTL_VERIFICATION
Interested candidates can share their profiles to anithaakula@juntrantech.com
Greetings from Juntran Technologies
We are hiring < 2020 #Trained_Freshers candidates in #vlsi domain for below requirements
#DESIGN_FOR_TESTABILITY
#DESIGN_AND_VERIFICATION
#RTL_VERIFICATION
Interested candidates can share their profiles to anithaakula@juntrantech.com
Greetings from SISOC Semiconductor Technologies Pvt Ltd!!
Hiring for hashtag#trained B TECH(2017,2018,2019 and 2020)/ MTECH(2017,2018,2019,2020 and 2021) hashtag#freshers
Eligibility: B Tech/BE (ECE/EEE) / MTech (VLSI/ECE) in hashtag#designverification (Trained or intern)
Open Position :
1.Verification Engineer
Work Location: Bangalore
Skills required :
1. Very Strong knowledge of System Verilog and UVM.
2. Good communication Skills.
3. Minimum 6 months Trained or intern in design verification.
Interested, Kindly share resumes to
mounika.immadi@sisocsemi.com
Hiring for hashtag#trained B TECH(2017,2018,2019 and 2020)/ MTECH(2017,2018,2019,2020 and 2021) hashtag#freshers
Eligibility: B Tech/BE (ECE/EEE) / MTech (VLSI/ECE) in hashtag#designverification (Trained or intern)
Open Position :
1.Verification Engineer
Work Location: Bangalore
Skills required :
1. Very Strong knowledge of System Verilog and UVM.
2. Good communication Skills.
3. Minimum 6 months Trained or intern in design verification.
Interested, Kindly share resumes to
mounika.immadi@sisocsemi.com