Greetings from SISOC Semiconductor Technologies Pvt Ltd!!
Hiring for hashtag#trained B TECH(2017,2018,2019 and 2020)/ MTECH(2017,2018,2019,2020 and 2021) hashtag#freshers
Eligibility: B Tech/BE (ECE/EEE) / MTech (VLSI/ECE) in hashtag#designverification (Trained or intern)
Open Position :
1.Verification Engineer
Work Location: Bangalore
Skills required :
1. Very Strong knowledge of System Verilog and UVM.
2. Good communication Skills.
3. Minimum 6 months Trained or intern in design verification.
Interested, Kindly share resumes to
mounika.immadi@sisocsemi.com
Hiring for hashtag#trained B TECH(2017,2018,2019 and 2020)/ MTECH(2017,2018,2019,2020 and 2021) hashtag#freshers
Eligibility: B Tech/BE (ECE/EEE) / MTech (VLSI/ECE) in hashtag#designverification (Trained or intern)
Open Position :
1.Verification Engineer
Work Location: Bangalore
Skills required :
1. Very Strong knowledge of System Verilog and UVM.
2. Good communication Skills.
3. Minimum 6 months Trained or intern in design verification.
Interested, Kindly share resumes to
mounika.immadi@sisocsemi.com
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7Rays Semiconductors India Private Limited, Great oppertunity to work full chip Design & Verification Trunky projects We're hiring for below positions.
1. hashtag#Designverification engineer with 5+ Years experise is hashtag#Systemverilog & hashtag#UVM for hashtag#Bangalore or hashtag#Noida Location.
2. hashtag#ASICRTL design engineers with 5+ Years experise in hashtag#AXI4 / hashtag#PCIE hashtag#IPdevelopment Good understanding of hashtag#PCIE TLP structures for hashtag#Bangalore or hashtag#Noida Location.
Interested engineers please share update resume to sridhar.jv@7rayssemi.com, or spread the work across which can help the interested engineers.
1. hashtag#Designverification engineer with 5+ Years experise is hashtag#Systemverilog & hashtag#UVM for hashtag#Bangalore or hashtag#Noida Location.
2. hashtag#ASICRTL design engineers with 5+ Years experise in hashtag#AXI4 / hashtag#PCIE hashtag#IPdevelopment Good understanding of hashtag#PCIE TLP structures for hashtag#Bangalore or hashtag#Noida Location.
Interested engineers please share update resume to sridhar.jv@7rayssemi.com, or spread the work across which can help the interested engineers.
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We are hiring RTL hashtag#DesignVerification Engineers for our Controller IP R&D Team at Cadence, Noida.
Experience: 10-15 Years (Multiple positions)
Qualification: B.Tech/M.Tech (EE/EC/CS)
Mandatory Skills: Strong SV/UVM/Testbench development skills with working knowledge of PCIe, CXL, Ethernet or similar protocols.
Send your resume to: cdn_dip_hiring@cadence.com with Subject "RTL Verification Noida | Experience: <#> Yrs"
Experience: 10-15 Years (Multiple positions)
Qualification: B.Tech/M.Tech (EE/EC/CS)
Mandatory Skills: Strong SV/UVM/Testbench development skills with working knowledge of PCIe, CXL, Ethernet or similar protocols.
Send your resume to: cdn_dip_hiring@cadence.com with Subject "RTL Verification Noida | Experience: <#> Yrs"
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https://www.linkedin.com/posts/pratyush-verificationengineer_search-jobs-google-careers-activity-7324763732239175680-VASS/
you can dm him for referral at google
you can dm him for referral at google
Linkedin
Google currently has multiple open positions for Design Verification and RTL Design roles across various teams! | Pratyush Patel
Google currently has multiple open positions for Design Verification and RTL Design roles across various teams!
If you are interseted in the below openings, feel free to DM me your resume.
Openings :
Design Verificaiton Engineer : https://lnkd.in/dMjwJQik…
If you are interseted in the below openings, feel free to DM me your resume.
Openings :
Design Verificaiton Engineer : https://lnkd.in/dMjwJQik…
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We are hiring RTL
hashtag
#DesignVerification Engineers for our Digital IP R&D Team at Cadence, Noida/Bangalore.
Experience: 8-12 Years (Multiple positions)
Qualification: B.Tech/M.Tech (EE/EC/CS)
Mandatory Skills: Strong SV/UVM/Testbench development skills with working knowledge of PCIe, CXL, USB, Ethernet or similar protocols.
Send your resume to: cdn_dip_hiring@cadence.com with Subject "RTL Verification | Experience: <#> Yrs | Location: <Noida or Bangalore>"
hashtag
#DesignVerification Engineers for our Digital IP R&D Team at Cadence, Noida/Bangalore.
Experience: 8-12 Years (Multiple positions)
Qualification: B.Tech/M.Tech (EE/EC/CS)
Mandatory Skills: Strong SV/UVM/Testbench development skills with working knowledge of PCIe, CXL, USB, Ethernet or similar protocols.
Send your resume to: cdn_dip_hiring@cadence.com with Subject "RTL Verification | Experience: <#> Yrs | Location: <Noida or Bangalore>"
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7Rays Semiconductors India Private Limited Hiring | hashtag #DesignVerification Engineer | 4+ Years | hashtag #Bangalore
Are you a hashtag #DV expert with a passion for building robust, scalable hashtag #testbenches and writing complex hashtag#testcases in hashtag#SystemVerilog and hashtag#UVM?
This is your chance to be part of cutting-edge VLSI projects that are shaping the next generation of silicon — from AI/ML accelerators to high-performance SoCs.
📩 Apply by clicking below jobs / Share resume to sridhar.jv@7rayssemi.com
Are you a hashtag #DV expert with a passion for building robust, scalable hashtag #testbenches and writing complex hashtag#testcases in hashtag#SystemVerilog and hashtag#UVM?
This is your chance to be part of cutting-edge VLSI projects that are shaping the next generation of silicon — from AI/ML accelerators to high-performance SoCs.
📩 Apply by clicking below jobs / Share resume to sridhar.jv@7rayssemi.com
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