We are hiring RTL
hashtag
#DesignVerification Engineers for our Digital IP R&D Team at Cadence, Noida/Bangalore.
Experience: 8-12 Years (Multiple positions)
Qualification: B.Tech/M.Tech (EE/EC/CS)
Mandatory Skills: Strong SV/UVM/Testbench development skills with working knowledge of PCIe, CXL, USB, Ethernet or similar protocols.

Send your resume to: cdn_dip_hiring@cadence.com with Subject "RTL Verification | Experience: <#> Yrs | Location: <Noida or Bangalore>"