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Recent Interview Questions for DV

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Share resume at aman-singh1@hcltech.com

We NextGenSilicon Technologies Pvt Ltd are hiring DFT Engineers in Bangalore with 3–7 years of experience.
Key skills: Scan insertion, ATPG, MBIST, JTAG, and hands-on with industry tools (Synopsys / Cadence / Mentor).
📍 Location: Bangalore
⏱️ Notice Period: Immediate to 30 days preferred
If you are open to exploring this opportunity, please share your updated CV to saipreethi.tatireddy@nextgensilicon.com

We’re Hiring: Design Engineer – DV (2+ yrs hands-on experience)
Company: Truechip Solutions Pvt. Ltd.
Location: Noida / Bangalore

What You’ll Do:
Work on IP/SoC verification and VIP development.
Build and maintain hands-on testbenches, automation scripts, and verification environments.
Debug RTL issues, optimize verification flows, and collaborate with cross-functional teams.

Skills We’re Looking For:
C / C++, Python / Shell scripting with practical implementation experience.
Verilog / SystemVerilog / UVM / OVM applied in real DV projects.
Linux and version control (Git / Perforce) for daily verification tasks.
Strong understanding of digital electronics and semiconductor fundamentals

Why Join Truechip?
Work on cutting-edge IP/SoC projects.
Hands-on exposure to DV methodologies and verification frameworks.
Grow under experienced mentors in a fast-paced semiconductor environment.

Apply Now: diksha10602@truechip.net

🚀 We’re Hiring: Physical Verification Engineer
📍 Location: Bangalore
💼 Experience: 0–3 Years
🕒 Notice Period: Immediate to 1 Month

Are you passionate about VLSI and eager to begin your journey in Physical Verification?
We’re looking for talented engineers with hands-on experience in Innovus to join our dynamic team!

🔍 Key Responsibilities:
🔸 Run Design Rule Checking (DRC) using industry-standard tools and collaborate with layout designers to resolve issues.
🔸 Perform Layout vs. Schematic (LVS) checks to ensure design accuracy.
🔸 Conduct Electrical Rule Checking (ERC) to verify electrical integrity.
🔸 Work on Design for Manufacturing (DFM) and Process Technology Calibration.
🔸 Implement Resolution Enhancement Techniques (RET) and Fill Insertion.
🔸 Handle Multi-patterning, Hotspot Analysis, and Post-processing simulations.
🔸 Collaborate with process integration teams for smooth fabrication integration.
🔸 Maintain detailed documentation of verification processes and methodologies..

✨ Good to have
🔸Experience with Cadence Innovus tool is mandatory.

If you’re ready to grow your career in the semiconductor domain, we’d love to hear from you!

📩 Interested candidates can share their resume at - pranjali@digicomm.org

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