๐ We Are Hiring! Multiple Opportunities at Mirafra Technologies ๐
๐ Locations:
๐บ๐ธ USA: Cupertino (Bay Area), San Jose, San Diego, Irvine โ California
๐ช๐บ Europe: Germany
๐ฎ๐ณ India: Bangalore, Hyderabad, Noida | WFH Options for Select Roles
โณ Notice Period: 0โ90 days (varies by role)
๐ Open Positions:
๐บ๐ธ USA Roles:
1๏ธโฃ Senior Design Verification Engineer
Experience: 5+ Years in Design Verification
Location: Cupertino (Bay Area), San Jose, San Diego, Irvine โ California
Requirements: Valid USA Work Authorization (Engineers from any location can apply)
๐ช๐บ Europe Roles:
2๏ธโฃ Design Verification Engineers
Location: Germany
Experience: 5+ Years
Must-Have: Specman Expertise
๐ฎ๐ณ India Roles:
3๏ธโฃ Design Verification Engineers
PCIe โ 5+ Years (Bangalore/Hyderabad)
FUSA/NOC โ 3+ Years (Bangalore/Hyderabad)
UFS โ 4+ Years (WFH/Any Location)
DDR โ 5+ Years (WFH/Any Location)
IP/SoC (ARM-Based) โ 3+ Years (Noida)
Ethernet โ 3+ Years (Noida)
HSIO โ 5+ Years (Bangalore/Hyderabad)
AMS Verification โ 3+ Years (Bangalore/Hyderabad)
Formal Verification โ 3+ Years (Bangalore)
ACE/CHI Expertise โ 5+ Years (Bangalore)
4๏ธโฃ Post Silicon Validation Engineers
Experience: 3+ Years
Locations: Bangalore, Hyderabad, Noida
5๏ธโฃ DV Trainer
Location: Bangalore/Hyderabad
Expertise: SystemVerilog, UVM
๐ง Apply Now: Send your resume to pkalavathi@mirafra.com
๐ Referrals are welcome and much appreciated!
๐ Locations:
๐บ๐ธ USA: Cupertino (Bay Area), San Jose, San Diego, Irvine โ California
๐ช๐บ Europe: Germany
๐ฎ๐ณ India: Bangalore, Hyderabad, Noida | WFH Options for Select Roles
โณ Notice Period: 0โ90 days (varies by role)
๐ Open Positions:
๐บ๐ธ USA Roles:
1๏ธโฃ Senior Design Verification Engineer
Experience: 5+ Years in Design Verification
Location: Cupertino (Bay Area), San Jose, San Diego, Irvine โ California
Requirements: Valid USA Work Authorization (Engineers from any location can apply)
๐ช๐บ Europe Roles:
2๏ธโฃ Design Verification Engineers
Location: Germany
Experience: 5+ Years
Must-Have: Specman Expertise
๐ฎ๐ณ India Roles:
3๏ธโฃ Design Verification Engineers
PCIe โ 5+ Years (Bangalore/Hyderabad)
FUSA/NOC โ 3+ Years (Bangalore/Hyderabad)
UFS โ 4+ Years (WFH/Any Location)
DDR โ 5+ Years (WFH/Any Location)
IP/SoC (ARM-Based) โ 3+ Years (Noida)
Ethernet โ 3+ Years (Noida)
HSIO โ 5+ Years (Bangalore/Hyderabad)
AMS Verification โ 3+ Years (Bangalore/Hyderabad)
Formal Verification โ 3+ Years (Bangalore)
ACE/CHI Expertise โ 5+ Years (Bangalore)
4๏ธโฃ Post Silicon Validation Engineers
Experience: 3+ Years
Locations: Bangalore, Hyderabad, Noida
5๏ธโฃ DV Trainer
Location: Bangalore/Hyderabad
Expertise: SystemVerilog, UVM
๐ง Apply Now: Send your resume to pkalavathi@mirafra.com
๐ Referrals are welcome and much appreciated!