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Company Name: Synopsys
Post Name: ASIC Physical Design Engr
Expected Salary: up to โน15 LPA*
Job Location: Bengaluru
โ Apply Link: https://job4freshers.co.in/physical-design-job-at-synopsys/
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Post Name: ASIC Physical Design Engr
Expected Salary: up to โน15 LPA*
Job Location: Bengaluru
โ Apply Link: https://job4freshers.co.in/physical-design-job-at-synopsys/
Join our WhatsApp Group๐
https://chat.whatsapp.com/HPwYoHRh4ocALdolO64wNq
For Direct mails and job links join๐๐ป
https://telegram.dog/careerwithasr
How. to Apply for Job๐๐ป
https://youtu.be/WgSpskMXq04
Share This opportunity with your Friends and WhatsApp Groupโค๏ธ
Job4freshers
ASIC Physical Design job at Synopsys Off Campus 2025 | Apply Now! | Job4freshers
Synopsys Physical Design Off Campus 2025: Synopsys a leading company, is set to conduct an Off Campus Drive in 2025, offering opportunities for freshers to
Vikarna Technologies:
We're Hiring! VLSI Design & Verification Engineers ๐
Role Details
Domain: Design Verification (DV)
Experience: Freshers
Location: Bangalore
Job Description
Join our team as a VLSI Design and Verification Engineer! You will:
Verify and validate complex VLSI designs.
Develop testbenches and write test cases.
Ensure the correctness of designs at various stages.
How to Apply https://vikarnatechnologies.com/current-openings-1 Subject Line mention : Design Verification
We're Hiring! VLSI Design & Verification Engineers ๐
Role Details
Domain: Design Verification (DV)
Experience: Freshers
Location: Bangalore
Job Description
Join our team as a VLSI Design and Verification Engineer! You will:
Verify and validate complex VLSI designs.
Develop testbenches and write test cases.
Ensure the correctness of designs at various stages.
How to Apply https://vikarnatechnologies.com/current-openings-1 Subject Line mention : Design Verification
Vikarna Technologies
Where Passion Meets Career
๐ We Are Hiring! Multiple Opportunities at Mirafra Technologies ๐
๐ Locations:
๐บ๐ธ USA: Cupertino (Bay Area), San Jose, San Diego, Irvine โ California
๐ช๐บ Europe: Germany
๐ฎ๐ณ India: Bangalore, Hyderabad, Noida | WFH Options for Select Roles
โณ Notice Period: 0โ90 days (varies by role)
๐ Open Positions:
๐บ๐ธ USA Roles:
1๏ธโฃ Senior Design Verification Engineer
Experience: 5+ Years in Design Verification
Location: Cupertino (Bay Area), San Jose, San Diego, Irvine โ California
Requirements: Valid USA Work Authorization (Engineers from any location can apply)
๐ช๐บ Europe Roles:
2๏ธโฃ Design Verification Engineers
Location: Germany
Experience: 5+ Years
Must-Have: Specman Expertise
๐ฎ๐ณ India Roles:
3๏ธโฃ Design Verification Engineers
PCIe โ 5+ Years (Bangalore/Hyderabad)
FUSA/NOC โ 3+ Years (Bangalore/Hyderabad)
UFS โ 4+ Years (WFH/Any Location)
DDR โ 5+ Years (WFH/Any Location)
IP/SoC (ARM-Based) โ 3+ Years (Noida)
Ethernet โ 3+ Years (Noida)
HSIO โ 5+ Years (Bangalore/Hyderabad)
AMS Verification โ 3+ Years (Bangalore/Hyderabad)
Formal Verification โ 3+ Years (Bangalore)
ACE/CHI Expertise โ 5+ Years (Bangalore)
4๏ธโฃ Post Silicon Validation Engineers
Experience: 3+ Years
Locations: Bangalore, Hyderabad, Noida
5๏ธโฃ DV Trainer
Location: Bangalore/Hyderabad
Expertise: SystemVerilog, UVM
๐ง Apply Now: Send your resume to pkalavathi@mirafra.com
๐ Referrals are welcome and much appreciated!
๐ Locations:
๐บ๐ธ USA: Cupertino (Bay Area), San Jose, San Diego, Irvine โ California
๐ช๐บ Europe: Germany
๐ฎ๐ณ India: Bangalore, Hyderabad, Noida | WFH Options for Select Roles
โณ Notice Period: 0โ90 days (varies by role)
๐ Open Positions:
๐บ๐ธ USA Roles:
1๏ธโฃ Senior Design Verification Engineer
Experience: 5+ Years in Design Verification
Location: Cupertino (Bay Area), San Jose, San Diego, Irvine โ California
Requirements: Valid USA Work Authorization (Engineers from any location can apply)
๐ช๐บ Europe Roles:
2๏ธโฃ Design Verification Engineers
Location: Germany
Experience: 5+ Years
Must-Have: Specman Expertise
๐ฎ๐ณ India Roles:
3๏ธโฃ Design Verification Engineers
PCIe โ 5+ Years (Bangalore/Hyderabad)
FUSA/NOC โ 3+ Years (Bangalore/Hyderabad)
UFS โ 4+ Years (WFH/Any Location)
DDR โ 5+ Years (WFH/Any Location)
IP/SoC (ARM-Based) โ 3+ Years (Noida)
Ethernet โ 3+ Years (Noida)
HSIO โ 5+ Years (Bangalore/Hyderabad)
AMS Verification โ 3+ Years (Bangalore/Hyderabad)
Formal Verification โ 3+ Years (Bangalore)
ACE/CHI Expertise โ 5+ Years (Bangalore)
4๏ธโฃ Post Silicon Validation Engineers
Experience: 3+ Years
Locations: Bangalore, Hyderabad, Noida
5๏ธโฃ DV Trainer
Location: Bangalore/Hyderabad
Expertise: SystemVerilog, UVM
๐ง Apply Now: Send your resume to pkalavathi@mirafra.com
๐ Referrals are welcome and much appreciated!