7Rays Semiconductors India Private Limited, Great oppertunity to work full chip Design & Verification Trunky projects We're hiring for below positions.

1. hashtag#Designverification engineer with 5+ Years experise is hashtag#Systemverilog & hashtag#UVM for hashtag#Bangalore or hashtag#Noida Location.

2. hashtag#ASICRTL design engineers with 5+ Years experise in hashtag#AXI4 / hashtag#PCIE hashtag#IPdevelopment Good understanding of hashtag#PCIE TLP structures for hashtag#Bangalore or hashtag#Noida Location.

Interested engineers please share update resume to sridhar.jv@7rayssemi.com, or spread the work across which can help the interested engineers.

We at Analog Devices are having a few open position. Below are the details.
If in case you find a suitable position you can mail the details and your CV on shankar.mareboina@analog.com for referral.

Wipro DV interview Questions

1) Write a constraint where you have a 32 bit value bit [31:0] val where you’d want to
randomize this to where every randomization would only allow 2 bits to differ from the previous randomization.

2) write constraint that generates an array where odd indexed locations store even data and even indexed locations store odd data.

3) Write constraint that generates a 32-bit value (val) with requirements—50% even numbers, 20% values between 1K and 2K, and the remaining 30% as random values

Samsung Semiconductors India Research is Hiring Design Verification Engineers!!

Location: Bangalore

Interested candidates please share your updated resumes to s.amin@partner.samsung.com

Job Description:
• Knowledge in one or more Domains: PCI, CMOS, Display I/F, Memory, CPU, GPU, Sensor, SOC, IP
• Knowledge in various peripherals controllers and interfaces – Ethernet, PCI, PCIe, DP, UART, I2C, I2S, SPI, USB, PCI(e)