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We are hiring for multiple exciting positions across various locations!
1.Physical Design (P&R, Fullchip) - San Jose, CA
2.FPGA RTL ( Video ) - San Diego, CA
3.Embedded Multimedia (Streaming, DRM) - Dallas, TX
4.Embedded C++ (TV, STB) - Shenzhen, China
5.PCIe/ CXL Verification - India
6.Physical Design with RTL synthesis - India
7.Hardware Emulation (Palladium with AVIP) - India
8.Android
Engineer (NDK, C++) - NJ
If you are interested or know someone who may be interested, please can reach out to me at b.rajesh@mobiveil.co.in
1.Physical Design (P&R, Fullchip) - San Jose, CA
2.FPGA RTL ( Video ) - San Diego, CA
3.Embedded Multimedia (Streaming, DRM) - Dallas, TX
4.Embedded C++ (TV, STB) - Shenzhen, China
5.PCIe/ CXL Verification - India
6.Physical Design with RTL synthesis - India
7.Hardware Emulation (Palladium with AVIP) - India
8.Android
Engineer (NDK, C++) - NJ
If you are interested or know someone who may be interested, please can reach out to me at b.rajesh@mobiveil.co.in
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We are hiring one GET, BE/ B Tech, Electrical and Electronics Engineering students, completed in year 2023/2024, from good acedamic background, from reputed institutions can sent your resumes to my email :
arthanarieswaran.Panchanathan.tn@mhi.com
Remuneration will be 6 LPA. Suitable for Candidates who are desirous of developing their carriers in Core and Power Plant Engineering
arthanarieswaran.Panchanathan.tn@mhi.com
Remuneration will be 6 LPA. Suitable for Candidates who are desirous of developing their carriers in Core and Power Plant Engineering
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SocBridge is hiring for DV engineers.
Skills: Verilog, SV & UVM
Eligibility: B.TECH/B.E & M.TECH/M.E
Experience: 1-8+ Yrs
Interested can share your Resume to hr@socbridgesemi.com
Skills: Verilog, SV & UVM
Eligibility: B.TECH/B.E & M.TECH/M.E
Experience: 1-8+ Yrs
Interested can share your Resume to hr@socbridgesemi.com
Mirafra Technologies #Hiring #DFT_DIRECTOR at #Bengaluru Location.
Please find the Job description Below:
Position: DFT Director – Design for Testability (DFT)
Location: Bangalore
Experience Level: 14+ years in semiconductor design, with extensive expertise in DFT methodologies
About the Role
We are seeking a seasoned leader to spearhead our Design for Testability (DFT) division. The DFT Director will play a pivotal role in defining, developing, and growing our DFT capabilities, ensuring we remain at the forefront of semiconductor design services. This individual will oversee project delivery, team development, and client engagement, driving excellence and innovation in DFT methodologies.
Key Qualifications:
Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
14+ years of experience in semiconductor design, with at least 5 years in a leadership role focusing on DFT.
Deep expertise in DFT methodologies, including:
Scan-based testing, ATPG, and fault simulation.
Built-In Self-Test (BIST) techniques.
Test compression and low-power testing.
DFT for hierarchical and multi-die designs.
Proven track record of successful client engagements and project delivery.
Strong leadership, communication, and business acumen.
Familiarity with industry-standard tools such as Mentor Tessent Synopsys Tetramax, , or Cadence Modus.
Preferred Skills:
Experience with multi-site and global team management.
Hands-on experience with post-silicon debug and ATE testing.
Strong understanding of emerging trends in AI-driven test automation and DFT for advanced nodes (e.g., 5nm, 3nm).
Interested candidates can share resume at sayantikamajumdar@mirafra.com
Please find the Job description Below:
Position: DFT Director – Design for Testability (DFT)
Location: Bangalore
Experience Level: 14+ years in semiconductor design, with extensive expertise in DFT methodologies
About the Role
We are seeking a seasoned leader to spearhead our Design for Testability (DFT) division. The DFT Director will play a pivotal role in defining, developing, and growing our DFT capabilities, ensuring we remain at the forefront of semiconductor design services. This individual will oversee project delivery, team development, and client engagement, driving excellence and innovation in DFT methodologies.
Key Qualifications:
Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
14+ years of experience in semiconductor design, with at least 5 years in a leadership role focusing on DFT.
Deep expertise in DFT methodologies, including:
Scan-based testing, ATPG, and fault simulation.
Built-In Self-Test (BIST) techniques.
Test compression and low-power testing.
DFT for hierarchical and multi-die designs.
Proven track record of successful client engagements and project delivery.
Strong leadership, communication, and business acumen.
Familiarity with industry-standard tools such as Mentor Tessent Synopsys Tetramax, , or Cadence Modus.
Preferred Skills:
Experience with multi-site and global team management.
Hands-on experience with post-silicon debug and ATE testing.
Strong understanding of emerging trends in AI-driven test automation and DFT for advanced nodes (e.g., 5nm, 3nm).
Interested candidates can share resume at sayantikamajumdar@mirafra.com
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