Mediatek Bangalore is hiring for the below positions:
->DFT Engineer (3-15 YOE)
->Physical Design Engineer (4-15 YOE)
->Analog Design Engineer (8-15 YOE)
->Physical Verification Engineer (5-15 YOE)
->UEFI Developer (5-15 YOE)
->Design Verification Engineer (3-15 YOE)
->CAD Design Engineer (5-15 YOE)
->AMS Verification Engineer (3-10 YOE)
If anyone is interested, please share your resume through DM or mail to garima.goyal@mediatek.com
->DFT Engineer (3-15 YOE)
->Physical Design Engineer (4-15 YOE)
->Analog Design Engineer (8-15 YOE)
->Physical Verification Engineer (5-15 YOE)
->UEFI Developer (5-15 YOE)
->Design Verification Engineer (3-15 YOE)
->CAD Design Engineer (5-15 YOE)
->AMS Verification Engineer (3-10 YOE)
If anyone is interested, please share your resume through DM or mail to garima.goyal@mediatek.com
HCLTech is Hiring โ ASIC/IP/SoC Verification Engineers ๐
Weโre expanding our Silicon Design & Engineering team and looking for experienced verification professionals who are passionate about building next-gen semiconductor solutions.
๐ Role: ASIC/IP/SoC Verification Engineer
๐ Locations: Bangalore | Hyderabad | Noida | Kochi | Chennai
๐ง Experience: 5 to 16 years
๐ Notice Period: 0 to 90 days
โ๏ธ Please do not share profiles with less than 5 years of experience.
๐ง Key Skills Weโre Looking For:
Strong expertise in SystemVerilog/UVM-based verification
Experience in IP/Subsystem/SoC level verification
Hands-on with simulation tools (VCS, Questa, etc.)
Familiarity with AMBA protocols (AXI, AHB, APB)
Debugging skills using waveform viewers and scripting (Python/Perl/TCL)
๐ฉ Interested or know someone who fits?
Send your resume or referrals to: aman-singh1@hcltech.com
Weโre expanding our Silicon Design & Engineering team and looking for experienced verification professionals who are passionate about building next-gen semiconductor solutions.
๐ Role: ASIC/IP/SoC Verification Engineer
๐ Locations: Bangalore | Hyderabad | Noida | Kochi | Chennai
๐ง Experience: 5 to 16 years
๐ Notice Period: 0 to 90 days
โ๏ธ Please do not share profiles with less than 5 years of experience.
๐ง Key Skills Weโre Looking For:
Strong expertise in SystemVerilog/UVM-based verification
Experience in IP/Subsystem/SoC level verification
Hands-on with simulation tools (VCS, Questa, etc.)
Familiarity with AMBA protocols (AXI, AHB, APB)
Debugging skills using waveform viewers and scripting (Python/Perl/TCL)
๐ฉ Interested or know someone who fits?
Send your resume or referrals to: aman-singh1@hcltech.com
โค3
Next Silicon Hiring Physical Design Engineer
https://www.nextsilicon.com/careers/india-physical-design-engineer?isComingFromApp=true&coref=1.11.p98_C515
https://www.nextsilicon.com/careers/india-physical-design-engineer?isComingFromApp=true&coref=1.11.p98_C515
Nextsilicon
Pioneering a radically new approach to HPC architecture that drives the industry forward by solving its biggest, most fundamental problems
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๐Why you should join:
๐ Stay updated with the latest job openings
๐ผ Access valuable interview questions.
๐ Take part in practice mock tests.
๐ฌ Weekly Q&A sessions.
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โค1
Meta Hiring Design Verification Engineer
Apply Link:
https://www.metacareers.com/jobs/724115943686074
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Apply Link:
https://www.metacareers.com/jobs/724115943686074
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Kinara Hiring ASIC Verification
Location: Hyderabad
Apply Now: https://kinara.ai/jobs/fresher-asic-verification/
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๐ Share with friends who might need this
Location: Hyderabad
Apply Now: https://kinara.ai/jobs/fresher-asic-verification/
Join our community for more โจโค๏ธ
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Kinara, Inc.
Fresher, ASIC Verification - Kinara, Inc.
Junior ASIC Verification Engineer Who we are Kinara is a Bay Area-based venture backed company. Our architecture is based on research done at Stanford University by Rehan Hameed and Wajahat Qadeer under the guidance of legendary Prof. Mark Horowitz (http://wwwโฆ
โค4
Hiring GLS Engineers at Capgemini Engineering ๐
We are looking for GLS engineers with 5+yrs of experience for Bangalore location.
Brief JD:
Total experience (5 -7 years) with SOC GLS experience of minimum 3+ years
hands on experience in GLS (Zero Delay, SDF, PAGLS)
Excellent debugging skills and fixing issues
Knowledge in SV/UVM and test bench flow
Good experience in EDA tools such as Synopsys Verdi, Cadence NC Sim.
Understanding of SOC Architecture
If interested, please share your profile to vinutha.r@capgemini.com
We are looking for GLS engineers with 5+yrs of experience for Bangalore location.
Brief JD:
Total experience (5 -7 years) with SOC GLS experience of minimum 3+ years
hands on experience in GLS (Zero Delay, SDF, PAGLS)
Excellent debugging skills and fixing issues
Knowledge in SV/UVM and test bench flow
Good experience in EDA tools such as Synopsys Verdi, Cadence NC Sim.
Understanding of SOC Architecture
If interested, please share your profile to vinutha.r@capgemini.com
Electronics Geek | Electrical and Electronics Job Updates / VLSI / embedded pinned ยซJoin the Electronics Geek community๐๐ป โ
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