Mirafra Technologies Hiring physical design manager role
Experience - 10+ years
Notice period- 0 to 90 days
Location - Bangalore
Must be Fullchip and Innovus expertise
Apply at sayantikamajumdar@mirafra.com
Ping me for detailed jd.
Experience - 10+ years
Notice period- 0 to 90 days
Location - Bangalore
Must be Fullchip and Innovus expertise
Apply at sayantikamajumdar@mirafra.com
Ping me for detailed jd.
Mirafra Technologies #Hiring #DFT_DIRECTOR at #Bengaluru Location.
Please find the Job description Below:
Position: DFT Director – Design for Testability (DFT)
Location: Bangalore
Experience Level: 14+ years in semiconductor design, with extensive expertise in DFT methodologies
About the Role
We are seeking a seasoned leader to spearhead our Design for Testability (DFT) division. The DFT Director will play a pivotal role in defining, developing, and growing our DFT capabilities, ensuring we remain at the forefront of semiconductor design services. This individual will oversee project delivery, team development, and client engagement, driving excellence and innovation in DFT methodologies.
Key Qualifications:
Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
14+ years of experience in semiconductor design, with at least 5 years in a leadership role focusing on DFT.
Deep expertise in DFT methodologies, including:
Scan-based testing, ATPG, and fault simulation.
Built-In Self-Test (BIST) techniques.
Test compression and low-power testing.
DFT for hierarchical and multi-die designs.
Proven track record of successful client engagements and project delivery.
Strong leadership, communication, and business acumen.
Familiarity with industry-standard tools such as Mentor Tessent Synopsys Tetramax, , or Cadence Modus.
Preferred Skills:
Experience with multi-site and global team management.
Hands-on experience with post-silicon debug and ATE testing.
Strong understanding of emerging trends in AI-driven test automation and DFT for advanced nodes (e.g., 5nm, 3nm).
Interested candidates can share resume at sayantikamajumdar@mirafra.com
You can reach out to me at +91 - 9007115796.
Please find the Job description Below:
Position: DFT Director – Design for Testability (DFT)
Location: Bangalore
Experience Level: 14+ years in semiconductor design, with extensive expertise in DFT methodologies
About the Role
We are seeking a seasoned leader to spearhead our Design for Testability (DFT) division. The DFT Director will play a pivotal role in defining, developing, and growing our DFT capabilities, ensuring we remain at the forefront of semiconductor design services. This individual will oversee project delivery, team development, and client engagement, driving excellence and innovation in DFT methodologies.
Key Qualifications:
Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
14+ years of experience in semiconductor design, with at least 5 years in a leadership role focusing on DFT.
Deep expertise in DFT methodologies, including:
Scan-based testing, ATPG, and fault simulation.
Built-In Self-Test (BIST) techniques.
Test compression and low-power testing.
DFT for hierarchical and multi-die designs.
Proven track record of successful client engagements and project delivery.
Strong leadership, communication, and business acumen.
Familiarity with industry-standard tools such as Mentor Tessent Synopsys Tetramax, , or Cadence Modus.
Preferred Skills:
Experience with multi-site and global team management.
Hands-on experience with post-silicon debug and ATE testing.
Strong understanding of emerging trends in AI-driven test automation and DFT for advanced nodes (e.g., 5nm, 3nm).
Interested candidates can share resume at sayantikamajumdar@mirafra.com
You can reach out to me at +91 - 9007115796.
Qualcomm is hiring Physical design engineers at Lead/staff/Sr.staff level.🔥
If you are ready to be part of our innovative team, submit your resume/CV today to keerkart@qti.qualcomm.com
If you are ready to be part of our innovative team, submit your resume/CV today to keerkart@qti.qualcomm.com
Hi All,
hiring for VLSI Engineer
PD hashtag#DV #DFT #Memorylayout Engineers
#Location: #Bangalore
Notice period : immediate
Interested Engineers, Please share your profile to deepika.poojary@acldigital.com .
hiring for VLSI Engineer
PD hashtag#DV #DFT #Memorylayout Engineers
#Location: #Bangalore
Notice period : immediate
Interested Engineers, Please share your profile to deepika.poojary@acldigital.com .
UVM_Questions
1. What is create and how it works
2. What is type_id
3. What is seq.start(null)
4. What is m_sequencer and p_sequencer
5. Virtual sequence
6. Advance concept of sequence start
7. Overide methods in the UVM
8. How the test starts and how it works
9. What is $sformstf and how does it works
10. Get_response and how does it work
11. `uvm_do and other functionality
1. What is create and how it works
2. What is type_id
3. What is seq.start(null)
4. What is m_sequencer and p_sequencer
5. Virtual sequence
6. Advance concept of sequence start
7. Overide methods in the UVM
8. How the test starts and how it works
9. What is $sformstf and how does it works
10. Get_response and how does it work
11. `uvm_do and other functionality
Mirafra hiring below positions
1. Physical verification - Noida
2. DFT - Chennai
3. Pd / sta - Chennai
Experience - 3 to 5 years
Np - 0 to 30 days
Apply at sayantikamajumdar@mirafra.com
Call or whatsapp at 9007115796
1. Physical verification - Noida
2. DFT - Chennai
3. Pd / sta - Chennai
Experience - 3 to 5 years
Np - 0 to 30 days
Apply at sayantikamajumdar@mirafra.com
Call or whatsapp at 9007115796